Fail-safe interface circuit
专利名称：Fail-safe interface circuit 发明人：ヘドベルグ，マッツ
申请号：JP1998505603
申请日：19970711
公开号：JP4181635B2
公开日：
20081119
专利内容由知识产权出版社提供
摘要： (57) is a fail-safe interface circuit including (1) a semiconductor switching circuit of at least one comprising a (6) a control terminal (4) (2), the second link pin [Abstract] The first link pin. By connecting each came with (2,4) second link terminal and first and second circuit to the first (8, 10), 1 either (6) of the terminal link (2,4) control terminal I is raised above the threshold potential difference between one is predetermined. Between the power supply of the interface circuit is cut, to prevent current flow all the opposite direction the first circuit (8) or the second circuit (10) the second link terminal and a first (2, The maximum potential of 4) is fed back to active control terminal semiconductor switching circuit (1) to (6).
申请人：テレフオンアクチーボラゲツト エル エム エリクソン（パブル）
南波瑠地址：スウーデン国エス―１２６ ２５ ストツクホルム（番地なし）
代理人：浅村 皓，浅村 肇，林 鉐三，清水 邦明
更多信息请下载全文后查看

版权声明：本站内容均来自互联网，仅供演示用，请勿用于商业和其他非法用途。如果侵犯了您的权益请与我们联系QQ:729038198，我们将在24小时内删除。