DATA SHEET
Objective specification
File under Integrated Circuits, IC01July 1993
TDA1313; TDA1313T
Stereo continuous calibration DAC (CC-DAC)
查询TDA1313供应商
Stereo continuous calibration DAC (CC-DAC)
TDA1313; TDA1313T
FEATURES
•4/8×oversampling (multiplexed/simultaneous input)possible
•Voltage output (capable of driving headphone)•Space saving package (SO16 or DIL16)•Low power consumption
•Wide dynamic range (16-bit resolution)•Continuous Calibration concept •Easy application:
–single 3 to 5.5 V supply rail
–output voltage is proportional to the supply voltage –integrated current-to-voltage converter
•Internal bias current ensures maximum dynamic range •Wide operating temperature range (−40°C to +85 °C)•Compatible with most current Japanese input format multiplexed/simultaneous, two's complement and CMOS)•No zero crossing distortion •Cost efficient
•High signal-to-noise ratio •Low total harmonic distortion.GENERAL DESCRIPTION
The TDA1313; 1313T is a voltage driven digital-to-analog converter, and is of a new generation of DACs which incorporates the innovative technique of Continuous Calibration (CC). The largest bit-currents are repeatedly generated from one single current reference source. This duplication is based upon an internal charge storage principle having an accuracy which is insensitive to ageing, temperature and process variations.
The TDA1313; 1313T is fabricated in a 1.0µm CMOS process and features an extremely low power dissipation,small package size and easy application. Furthermore, the accuracy of the intrinsic high c
oarse-current combined with the implemented symmetrical offset decoding method preclude zero-crossing distortion and ensures high quality audio reproduction. Therefore, the CC-DAC is eminently suitable for use in (portable) digital audio equipment.
ORDERING INFORMATION Notes
1.SOT38-1; 1996August 15.
2.SOT109-1; 1996August 15.
EXTENDED TYPE NUMBER
PACKAGE
PINS PIN POSITION
MATERIAL CODE TDA1313(1)16DIL plastic SOT38GG TDA1313T (2)
16
SO16
独生子女将无法继承父母房产plastic
SOT109AG
(CC-DAC)
TDA1313; TDA1313T
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS MIN.TYP.MAX.UNIT V DD supply voltage 3.0 5.0 5.5V
I DD supply current V DD = 5 V; at code
0000H
−89.5mA
V FS full scale output voltage V DD = 5 V 3.8 4.2 4.6V
(THD+N)/S total harmonic distortion
英文话剧剧本plus noise at 0 dB signal level−−88−81dB
−0.0040.009% at 0 dB signal level;
see Fig.8
−−70−dB
−0.03−% at−60 dB signal level−−36−28dB
− 1.6 4.0% at−60 dB; A-weighted−−38−dB
− 1.3−%
S/N signal-to-noise ratio at
bipolar zero A-weighted at code
0000H
9398−dB
t CS current setting time to
±1LSB
−0.2−µs
BR input bit rate at data input−−18.4Mbits/s f BCK clock frequency at clock
input
−−18.4MHz
TC FS full scale temperature
coefficient at analog outputs
(V OL; V OR)
−400−ppm
T amb operating ambient
韩国化妆品排行榜
temperature
−40−+85°C
P tot total power dissipation V DD = 5 V; at code
0000H
−4053mW
V DD = 3 V; at code
0000H
−15−mW
TDA1313; TDA1313T (CC-DAC)
(CC-DAC)
TDA1313; TDA1313T
PINNING
SYMBOL PIN DESCRIPTION
LRSEL/RSI1left/right select; right serial
input
SI/LSI2serial input; left serial input
4/8FSSEL34/8 oversampling select
V REF4reference voltage output
V SSO5operational amplifier ground
V DDO6operational amplifier supply
voltage
RIN7right analog input
ROUT8right analog output
高考体检项目有哪些 都检查什么LOUT9left analog output
LIN10left analog input
V DDA11analog supply voltage
V SSA12analog ground
V SSD13digital ground
爱你不需要理由V DDD14digital supply voltage
WS15word select BCK16bit clock input
Fig.2 Pin configuration. handbook, halfpage
TDA1313
TDA1313T
MGE229
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
LRSEL/RSI
SI/LSI
4/8FSSEL
V REF
V SSO
V DDO
RIN
ROUT LOUT
LIN
V DDA
V SSA
V SSD
V DDD
WS
BCK
FUNCTIONAL DESCRIPTION低值易耗品会计分录
The basic operation of the continuous calibration DAC is illustrated in Fig.3. The figure shows the calibration and operation cycle. During calibration of the MOS current source (Fig.3a) transistor M1 is connected as a diode by applying a reference current. The voltage V gs on the intrinsic gate-source capacitance C gs of M1 is then determined by the transistor characteristics. After calibration of the drain current to the reference value I REF, the switch S1 is opened and S2 is switched to the other position (Fig.3b). The gate-to-source voltage V gs of M1 is not changed because the charge on C gs is preserved. Therefore, the drain current of M1 will still be equal to I REF and this exact duplicate of I REF is now available at the I O terminal.
In the TDA1313; 1313T, 32 current sources and one spare current source are continuously calibrated (see Fig.1). The spare current source is included to allow continuous converter operation. The output of one calibrated source is connected to an 11-bit binary current devider which consists of 2048 transistors. A symmetrical offset decoding principle is incorporated and arranges the bit switching in such a way that the zero-crossing is performed by switching only the LSB currents.
The TDA1313; T (CC-DAC) accepts serial input data format of 16 bit word length. The most significant bit (bit 1) must always be first. The timing is illustrated in Fig.4 and the input data formats are illustrated in Figs 5 and 6.
Data is placed in the right and left input registers (Fig.1). The data in the input registers is simultaneously latched to the output registers which control the bit switches.
V REF and V FS are proportional to V DD.
Where: V DD1/V DD2 = V FS1/V = V REF1/V REF2
版权声明：本站内容均来自互联网，仅供演示用，请勿用于商业和其他非法用途。如果侵犯了您的权益请与我们联系QQ:729038198，我们将在24小时内删除。
发表评论